Various multilevel inverters including what is described in Patent Literature 1 have been suggested. FIG. 25 is a circuit diagram illustrating a configuration of one phase (referred to as a U phase) of a conventional single phase three level inverter.
Members indicated by reference numerals 101 and 102 are direct current power supplies. The direct current power supply 101 has a positive terminal which is connected to a direct current voltage terminal 101a and a negative terminal which is connected to a direct current voltage terminal 102a. The direct current power supply 101 applies a voltage of ½ V between the direct current voltage terminal 101a and the direct current voltage terminal 102a. The direct current power supply 102 has a positive terminal which is connected to the direct current voltage terminal 102a and a negative terminal which is connected to a direct current voltage terminal 103a. The direct current power supply 102 applies a voltage of ½ V between the direct current voltage terminal 102a and the direct current voltage terminal 103a. This causes the direct current voltage terminals 101a through 103a to have respective different direct current voltages.
An inverter arm 131 is provided between the direct current voltage terminals 101a through 103a and a U phase output terminal 106. The inverter arm 131 includes switching elements 111a through 114a which are connected in series and diodes 111b through 114b which are connected to the respective switching elements 111a through 114a in an opposite polarity and in parallel. The inverter arm 131 further includes a diode 121 whose anode is connected to the direct current voltage terminal 102a which is a direct current voltage dividing point and a diode 122 whose cathode is connected to the direct current voltage dividing point. The inverter arm 131 selectively carries out PWM (Pulse Width Modulation) control with respect to the switching elements 111a through 114a, so that a U phase voltage is outputted via the U phase output terminal 106.
Note that the diodes 111b through 114b thus connected in an opposite polarity and in parallel turn on when there is a phase difference between a line voltage vuw and an output current io.
FIG. 26 is a circuit diagram illustrating a configuration of the other phase (referred to as a W phase) of the conventional single phase three level inverter. The direct current power supplies 101 and 102 are shared by the U phase and the W phase. An inverter arm 132 is provided between the direct current voltage terminals 101a through 103a and a W phase output terminal 107. As in the case of the inverter arm 131 of U phase, the inverter arm 132 includes switching elements 115a through 118a which are connected in series and diodes 115b through 118b which are connected to the respective switching elements 115a through 118a in an opposite polarity and in parallel. The inverter arm 132 further includes a diode 123 whose anode is connected to the direct current voltage terminal 102a which is the direct current voltage dividing point and a diode 124 whose cathode is connected to the direct current voltage dividing point. The inverter arm 132 selectively carries out PWM control with respect to the switching elements 115a through 118a, so that a W phase voltage is outputted via the W phase output terminal 107.
FIG. 27 is a circuit diagram illustrating the conventional single phase three level inverter. The conventional single phase three level inverter of FIG. 27 is configured by combining the U phase circuit of FIG. 25 and the W phase circuit of FIG. 26.
The single phase three level inverter of FIG. 27 is arranged such that the line voltage vuw which is a voltage of a difference between the U phase voltage outputted via the U phase output terminal 106 and the W phase voltage outputted via the W phase output terminal 107 is supplied to a load which is connected between the U phase output terminal 106 and the W phase output terminal 107.
io in FIG. 27 refers to an output current. A waveform chart of FIG. 28 illustrates a waveform of the line voltage vuw for one (1) period. Circuit diagrams of FIGS. 29 through 32 illustrate states in which switching elements turn on/off.
The following description specifically discusses FIGS. 29 through 32. FIG. 29 is the circuit diagram illustrating the state in which the switching elements turn on/off during time periods (i) from t1 to t2 and (ii) from t3 to t4 in FIG. 28 in a case where the output current io is positive in the circuit of FIG. 27. FIG. 30 is the circuit diagram illustrating the state in which the switching elements turn on/off during a time period from t2 to t3 in FIG. 28 in the case where the output current io is positive in the circuit of FIG. 27. FIG. 31 is the circuit diagram illustrating the state in which the switching elements turn on/off during time periods (i) from t4 to t5 and (ii) from t6 to t7 in FIG. 28 in a case where the output current io is negative in the circuit of FIG. 27. FIG. 32 is the circuit diagram illustrating the state in which the switching elements turn on/off during a time period from t5 to t6 in FIG. 28 in the case where the output current io is negative in the circuit of FIG. 27.
Note that FIGS. 29 through 32 illustrate the states in which the switching elements turn on/off in a utility interactive inverter to which a load in which the line voltage vuw and the output current io are in phase with each other is connected.
The following description discusses how the conventional single phase three level inverter operates.
First, during a time period from t1 to t4 in FIG. 28, the inverter arm 131 of U phase causes the switching element 112a to turn on and the switching element 114a to turn off. The inverter arm 131 carries out PWM control with respect to the switching elements 111a and 113a such that the switching elements 111a and 113a have opposite polarities.
In contrast, the inverter arm 132 of W phase causes the switching element 115a to turn off and the switching element 117a to turn on. The inverter arm 132 carries out PWM control with respect to the switching elements 116a and 118a such that the switching elements 116a and 118a have opposite polarities.
Such switching control causes the state illustrated in FIG. 29 to repeatedly occur during the time periods (i) from t1 to t2 and (ii) from t3 to t4. Such switching control also causes the state illustrated in FIG. 30 to repeatedly occur during the time period from t2 to t3. Accordingly, the line voltage vuw has a waveform shown in the time period from t1 to t4 in FIG. 28.
Next, during a time period from t4 to t7 in FIG. 28, the inverter arm 131 of U phase causes the switching element 111a to turn off and the switching element 113a to turn on. The inverter arm 131 carries out PWM control with respect to the switching elements 112a and 114a such that the switching elements 112a and 114a have opposite polarities.
In contrast, the inverter arm 132 of W phase causes the switching element 116a to turn on and the switching element 118a to turn off. The inverter arm 132 carries out PWM control with respect to the switching elements 115a and 117a such that the switching elements 115a and 117a have opposite polarities.
Such switching control causes the state illustrated in FIG. 31 to repeatedly occur during the time periods (i) from t4 to t5 and (ii) from t6 to t7. Such switching control also causes the state illustrated in FIG. 32 to repeatedly occur during the time period from t5 to t6. Accordingly, the line voltage vuw has a waveform shown in the time period from t4 to t7 in FIG. 28.
The conventional single phase three level inverter of FIG. 27 thus controls one (1) period from t1 to t7. When finishing control of the one period, the conventional single phase three level inverter restarts controlling the one period at t1.
Conventional multilevel inverter-related examples include not only the multilevel inverter of Patent Literature 1 and the conventional single phase three level inverter of FIG. 27 but also a multilevel power inverter which is disclosed in Patent Literature 2 and whose neutral point is clamped. Patent Literature 3 discloses a bidirectional switch used in an inverter whose neutral point is clamped.